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<page pageid="88" ns="0" title="SDSL">
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<rev xml:space="preserve">== Overview ==
The stencil domain specific language (SDSL) is a domain-specific language for expressing stencil
computations. SDSL is loosely based on the
[http://scholar.google.com/scholar?cluster=14180165025443695396&hl=en&as_sdt=0,33 RNPL] and [http://scholar.google.com/scholar?cluster=6456210238832122937&hl=en&as_sdt=0,33 SNPL] languages used for
rapid prototyping of partial differential equation solvers, although the resemblance is mostly
cosmetic and no code is shared between the projects. The purpose of SDSL is to provide a programming language that allows for the specification of
non-trivial stencil computations in a form that enables the generation of high-performance
implementations that can be obtained in a performance-portable manner on multiple platforms.
SDSL can be embedded in C, C++, and MATLAB code. Currently, backends exist for generating (1) affine C99 code intended for further
optimization by polyhedral compiler tools including [[PolyOpt/C]] and
[http://pocc.sourceforge.net/ PoCC], (2) CUDA code with overlapped tiling optimizations as described by
[http://scholar.google.com/scholar?q=holewinski+overlapped+tiling+gpu&btnG=&hl=en&as_sdt=0%2C33 Holewinski, Pouchet, and Sadayappan], and (3) short-vector SIMD code for
SSE2, SSE4, AVX, Xeon Phi (experimental), and ARM NEON (experimental) vector ISA with [http://scholar.google.com/scholar?q=author%3Ahenretty+author%3Averas+author%3Apouchet+author%3Afranchetti+author%3Aramanujam+author%3Asadayappan+stencil+compiler+simd+architectures&btnG=&hl=en&as_sdt=0%2C36 split tiling] and [http://scholar.google.com/scholar?hl=en&q=author%3Ahenretty+author%3Astock+author%3Apouchet+author%3Afranchetti+author%3Aramanujam+author%3Asadayappan+data+layout+transformation+for+stencil+computations+simd+architectures&btnG=Search&as_sdt=0%2C36&as_ylo=&as_vis=0 DLT] optimizations.
== People ==
* [http://www.cse.ohio-state.edu/~henretty/ Tom Henretty]
* [http://www.linkedin.com/pub/justin-holewinski/43/990/7a9 Justin Holewinski]
* [http://web.cse.ohio-state.edu/~rawatp/ Prashant Rawat]
* [http://kevinstock.org Kevin Stock]
* [https://sites.google.com/site/nsedaghati/ Naser Sedaghati]
* [http://www.linkedin.com/pub/richard-veras/b/158/bb0 Richard Veras]
* [http://users.ece.cmu.edu/~franzf/ Franz Franchetti]
* [http://www.cs.ucla.edu/~pouchet/ Louis-Noël Pouchet]
* [http://www.ece.lsu.edu/jxr/ J. Ramanujam]
* [http://www.cse.ohio-state.edu/~ountev/ Atanas Rountev]
* [http://www.cse.ohio-state.edu/~saday/ P. Sadayappan]
== Publications ==
* T. Henretty, J. Holewinski, R. Veras, F. Franchetti, L.N. Pouchet, J. Ramanujam, A. Rountev, P. Sadayappan. “A Domain-Specific Language and Compiler for Stencil Computations on Short-Vector SIMD and GPU Architectures,” Compilers for Parallel Computing Workshop (CPC), July 2013. [http://www.cse.ohio-state.edu/~henretty/papers/henretty-cpc13.pdf link]
* T. Henretty, R. Veras, F. Franchetti, L.N. Pouchet, J. Ramanujam, P. Sadayappan. “A Stencil Compiler for Short-Vector SIMD Architectures,” International Conference on Supercomputing (ICS), June 2013. [http://scholar.google.com/scholar?q=author%3Ahenretty+author%3Averas+author%3Apouchet+author%3Afranchetti+author%3Aramanujam+author%3Asadayappan+stencil+compiler+simd+architectures&btnG=&hl=en&as_sdt=0%2C36 link]
* T. Henretty, J. Holewinski, N. Sedaghati, L.N. Pouchet, A. Rountev, P. Sadayappan. “Stencil Domain Specific Language (SDSL) User Guide,” Ohio State University Technical Report OSU-CISRC-4/13-TR09, 2013. [http://scholar.google.com/scholar?q=author%3Ahenretty+author%3Aholewinski+author%3Asedaghati+author%3Apouchet+author%3Arountev+author%3Asadayappan+Stencil+Domain+Specific+Language+User+Guide&btnG=&hl=en&as_sdt=0%2C36 link]
* J. Holewinski, L.N. Pouchet, P. Sadayappan. “High-Performance Code Generation for Stencil Computations on GPU Architectures,” International Conference on Supercomputing (ICS), June 2012. [http://scholar.google.com/scholar?cluster=1114458740422599619&hl=en&as_sdt=0,33 link]
* T. Henretty, K. Stock, L.N. Pouchet, F. Franchetti, J. Ramanujam and P. Sadayappan. "Data Layout Transformation for Stencil Computations on Short-Vector SIMD Architectures," International Conference on Compiler Construction (CC), March 2011. [http://scholar.google.com/scholar?hl=en&q=author%3Ahenretty+author%3Astock+author%3Apouchet+author%3Afranchetti+author%3Aramanujam+author%3Asadayappan+data+layout+transformation+for+stencil+computations+simd+architectures&btnG=Search&as_sdt=0%2C36&as_ylo=&as_vis=0 link]
== Downloads ==
* [http://hpcrl.cse.ohio-state.edu/sdslc/sdslc-0.3.2.tar.gz SDSLC 0.3.2]
** [http://hpcrl.cse.ohio-state.edu/sdslc/sdsl-guide-0.3.2.pdf User Guide]
** [http://hpcrl.cse.ohio-state.edu/sdslc/README-0.3.2.txt README]
** [http://hpcrl.cse.ohio-state.edu/sdslc/CHANGELOG-0.3.2.txt CHANGELOG]
* [http://hpcrl.cse.ohio-state.edu/sdslc/sdslc-0.2.2.tar.gz SDSLC 0.2.2]
** [http://hpcrl.cse.ohio-state.edu/sdslc/sdsl-guide-0.2.2.pdf User Guide]
** [http://hpcrl.cse.ohio-state.edu/sdslc/README-0.2.2.txt README]
== Acknowledgements ==
This work was supported in part by the U.S. National Science Foundation through awards 0811781, 0926127, 0926687, 0926688, and by the Center for Domain-Specific Computing (CDSC) funded by NSF "Expeditions in Computing" award 092617, by the U.S. Army through contract W911NF-10-1-0004, and by the U.S. Department of Energy through award DE-SC0005033.</rev>
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