PrimeTile

From HPCRL Wiki
Revision as of 16:57, 26 March 2014 by Hartonoa (Talk | contribs)
Jump to: navigation, search

Overview

Loop tiling, as one of the most important compiler optimization techniques, is beneficial for both parallel machines and uniprocessors. Efficient generation of multi-level tiled code is essential to maximize data reuse in deep memory hierarchies. Tiled loops with parameterized tile sizes (not compile time constants) enable runtime optimizations used in iterative compilation and automatic tuning. Previous parametric multi-level tiling approaches have been restricted to perfectly nested loops, where all statements are contained inside the innermost loop of a loop nest. Previous solutions to tiling for imperfect loop nests have been limited to the case where tile sizes are fixed. PrimeTile provides an effective way to generate efficient parameterized multi-level tiled code for imperfectly nested loops. The generated tiled code contains loops that iterate over full rectangular tiles, making them suitable for compiler optimizations such as register tiling.

Download

PrimeTile 0.2.0 (beta) (updated: March 25th, 2009)

PrimeTile 0.3.0 (beta -- prerelease) (for latest improvements, including register tiling support)

Personal tools